DYNAMIC ELECTRICAL CHARACTERISTICS LIN P" />
參數(shù)資料
型號(hào)： MCZ33905BD5EK
廠商： Freescale Semiconductor
文件頁數(shù)： 29/106頁
文件大小： 0K
描述： IC SBC CAN HS 5.0V 54SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 28 V
封裝/外殼： 54-SSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 54-SOICW-EP
包裝： 管件
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
33903/4/5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL
LAYER SPECIFICATION
BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . SEE Figure 18, PAGE 32.
Duty Cycle 1:
THREC(MAX) = 0.744 * VSUP
THDOM(MAX) = 0.581 * VSUP
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 s, 7.0 V VSUP18 V
D1
0.396
-
Duty Cycle 2:
THREC(MIN) = 0.422 * VSUP
THDOM(MIN) = 0.284 * VSUP
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 s, 7.6 V VSUP18 V
D2
-
0.581
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION
BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . MEASUREMENT THRESHOLDS. SEE Figure 19, PAGE 33.
Duty Cycle 3:
THREC(MAX) = 0.778 * VSUP
THDOM(MAX) = 0.616 * VSUP
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 s, 7.0 V VSUP18 V
D3
0.417
-
Duty Cycle 4:
THREC(MIN) = 0.389 * VSUP
THDOM(MIN) = 0.251 * VSUP
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 s, 7.6 V VSUP18 V
D4
-
0.590
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SRFAST
-
20
-
V/
s
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS
VSUP FROM 7.0 TO 18 V, BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . SEE Figure 18, PAGE 32.
Propagation Delay and Symmetry (See Figure 18, page 31 and Figure 19,
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
tREC_PD
tREC_SYM
-
-2.0
4.2
-
6.0
2.0
s
Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 20,
page 32 for LP VDD OFF mode and Figure 21, page 33 for LP mode)
tPROPWL
42
70
95
s
Bus Wake-up Event Reported
From LP VDD OFF mode
From LP VDD ON mode
tWAKE_LPVDD
OFF
tWAKE_LPVDD
ON
-
1.0
-
1500
12
s
TXD Permanent Dominant State Delay (Guaranteed by design)
tTXDDOM
0.65
1.0
1.35
s
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V
VSUP 28 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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