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參數(shù)資料
| 型號： | MCP6V26-E/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP AUTO-ZERO SGL 8MSOP |
| 標準包裝： | 100 |
| 放大器類型： | 自動調(diào)零 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 1 V/µs |
| 增益帶寬積： | 2MHz |
| 電流 - 輸入偏壓： | 7pA |
| 電壓 - 輸入偏移： | 2µV |
| 電流 - 電源： | 620µA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 管件 |
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MCP6V26/7/8
DS25007B-page 24
2011 Microchip Technology Inc.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
4.2.2
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V26/7/8
zero-drift op amps is VDD – 15 mV (minimum) and
VSS + 15 mV (maximum) when RL =10 kΩ is
connected to VDD/2 and VDD = 5.5V. Refer to
Figure 2-19 and Figure 2-20.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.2.3
CHIP SELECT (CS)
The single MCP6V28 has a Chip Select (CS) pin.
When CS is pulled high, the supply current for the
corresponding op amp drops to about 1 A (typical),
and is pulled through the CS pin to VSS. When this
happens, the amplifier is put into a high impedance
state. By pulling CS low, the amplifier is enabled. If the
CS pin is left floating, the internal pull-down resistor
(about 5 M
Ω) will keep the part on. Figure 1-4 shows
the output voltage and supply current response to a CS
pulse.
4.3
Application Tips
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2
DC GAIN PLOTS
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms
of the reciprocals (in units of V/V) of CMRR, PSRR
and AOL, respectively. They represent the change in
input offset voltage (VOS) with a change in common
mode input voltage (VCM), power supply voltage (VDD)
and output voltage (VOUT).
The 1/AOL histogram is centered near 0 V/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise, not unstable behavior. We validate the op amps’
stability by making multiple measurements of VOS; an
unstable part would fail, because it would show either
greater variability in VOS, or the output stuck at one of
the rails.
4.3.3
OFFSET AT POWER UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the startup time (like
tSTR).
It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
4.3.4
SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10
Ω
to 1 k
Ω at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances are needed for high gains.
Without them, parasitic capacitances can cause
positive feedback and instability.
4.3.5
SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match. Large
input capacitances and source resistances, together
with high gain, can lead to positive feedback and
instability.
V
OS TA
()
V
OS
TC
1ΔTTC2ΔT
2
++
=
Where:
ΔT=
TA –25°C
VOS(TA)
=
input offset voltage at TA
VOS
=
input offset voltage at +25°C
TC1
=
linear temperature coefficient
TC2
=
quadratic temperature
coefficient
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