參數(shù)資料
型號(hào)： MCP6V26-E/MS
廠商： Microchip Technology
文件頁(yè)數(shù)： 16/50頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP AUTO-ZERO SGL 8MSOP
標(biāo)準(zhǔn)包裝： 100
放大器類型： 自動(dòng)調(diào)零
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 1 V/µs
增益帶寬積： 2MHz
電流 - 輸入偏壓： 7pA
電壓 - 輸入偏移： 2µV
電流 - 電源： 620µA
電流 - 輸出 / 通道： 22mA
電壓 - 電源，單路/雙路(±)： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
2011 Microchip Technology Inc.
DS25007B-page 23
MCP6V26/7/8
4.2
Other Functional Blocks
4.2.1
RAIL-TO-RAIL INPUTS
The input stage of the MCP6V26/7/8 op amps use two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM,
which is approximately equal to VIN+ and VIN– in
normal operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD +0.2V,
and down to VSS – 0.15V, at +25°C (see Figure 2-18).
The input offset voltage (VOS) is measured at
VCM =VSS – 0.15V and VDD + 0.2V to ensure proper
operation.
The transition between the input stages occurs when
VCM ≈ VDD –1.2V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.
4.2.1.1
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages.
an
input voltage
exceeding both supplies with no phase inversion.
4.2.1.2
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings ). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize input bias
current (IB).
FIGURE 4-4:
Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that are well above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
FIGURE 4-5:
Protecting the Analog Inputs
Against High Voltages.
4.2.1.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute
This
requirement
is
independent of the voltage limits previously discussed.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad
VIN–
V1
VDD
D1
VOUT
V2
D2
U1
MCP6V2X
V1
R1
VDD
D1
min(R1,R2)>
VSS –min(V1,V2)
2mA
VOUT
V2
R2
D2
min(R1,R2)>
max(V1,V2)– VDD
2mA
U1
MCP6V2X
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