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參數(shù)資料
| 型號(hào)： | MCP6V11UT-E/LT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP SGL ZERO DRIFT SC70-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 零漂移 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.03 V/µs |
| 增益帶寬積： | 80kHz |
| 電流 - 輸入偏壓： | 5pA |
| 電壓 - 輸入偏移： | 8µV |
| 電流 - 電源： | 7.5µA |
| 電流 - 輸出 / 通道： | 17mA |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP（5 引線），SC-88A，SOT-353 |
| 供應(yīng)商設(shè)備封裝： | SC-70-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MCP6V11UT-E/LTDKR |
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2012 Microchip Technology Inc.
DS25124A-page 21
MCP6V11/1U
4.2.1.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute Maximum
Ratings ). This requirement is independent of the volt-
age limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
4.2.2
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V11/1U zero-drift
op amps is VDD –20mV (minimum) and VSS +20 mV
(maximum) when RL =10k is connected to VDD/2
for more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.3
Application Tips
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2
DC GAIN PLOTS
(in units of V/V) of CMRR, PSRR and AOL,
respectively. They represent the change in input offset
voltage (VOS) with a change in common mode input
voltage (VCM), power supply voltage (VDD) and output
voltage (VOUT).
The 1/AOL histogram is centered near 0 V/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise and tester limitations, not unstable behavior. Pro-
duction tests make multiple VOS measurements, which
validates an op amp's stability; an unstable part would
show greater VOS variability, or the output would stick
at one of the supply rails.
4.3.3
OFFSET AT POWER UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the startup time (like
tSTR).
It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
V1
R1
VDD
D1
min(R1,R2)>
VSS –min(V1,V2)
2mA
VOUT
V2
R2
D2
min(R1,R2)>
max(V1,V2)– VDD
2mA
U1
MCP6V1X
V
OS TA
()
V
OS
TC
1ΔTTC2ΔT
2
++
=
Where:
T=
TA –25°C
VOS(TA) = input offset voltage at TA
VOS = input offset voltage at +25°C
TC1 = linear temperature coefficient
TC2 = quadratic temperature coefficient
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