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| 型號(hào)： | MCP6V11UT-E/LT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP SGL ZERO DRIFT SC70-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 零漂移 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.03 V/µs |
| 增益帶寬積： | 80kHz |
| 電流 - 輸入偏壓： | 5pA |
| 電壓 - 輸入偏移： | 8µV |
| 電流 - 電源： | 7.5µA |
| 電流 - 輸出 / 通道： | 17mA |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP（5 引線），SC-88A，SOT-353 |
| 供應(yīng)商設(shè)備封裝： | SC-70-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MCP6V11UT-E/LTDKR |
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2012 Microchip Technology Inc.
DS25124A-page 19
MCP6V11/1U
4.0
APPLICATIONS
The MCP6V11/1U family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for precision applications with
requirements for small packages and low power. Its low
supply voltage and low quiescent current make the
MCP6V11/1U devices ideal for battery-powered
applications.
4.1
Overview of Zero-Drift Operation
Figure 4-1 shows a simplified diagram of the
MCP6V11/1U zero-drift op amps. This diagram will be
used to explain how slow voltage errors are reduced in
this architecture (much better VOS, VOS/TA (TC1),
CMRR, PSRR, AOL and 1/f noise).
FIGURE 4-1:
Simplified Zero-Drift Op
Amp Functional Diagram.
4.1.1
BUILDING BLOCKS
The Main Amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the low
frequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.
The Auxiliary Amplifier, Chopper Input Switches and
Chopper Output Switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequency.
The Low-Pass Filter reduces high frequency content,
including harmonics of the Chopping Clock.
The Output Buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The Oscillator runs at fOSC1 = 50 kHz. Its output is
divided by two, to produce the Chopping Clock rate of
fCHOP =25kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.
The Digital Control block controls switching and POR
events.
4.1.2
CHOPPING ACTION
Figure 4-2 shows the amplifier connections for the first
phase of the Chopping Clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.
FIGURE 4-2:
First Chopping Clock Phase;
Equivalent Amplifier Diagram.
FIGURE 4-3:
Second Chopping Clock
Phase; Equivalent Amplifier Diagram.
VIN+
VIN–
Main
Buffer
VOUT
VREF
Amp.
Output
NC
Aux.
Amp.
Chopper
Input
Switches
Chopper
Output
Switches
Oscillator
Low-Pass
Filter
POR
Digital Control
VIN+
VIN–
Main
Amp.
NC
Aux.
Amp.
Low-Pass
Filter
VIN+
VIN–
Main
Amp.
NC
Aux.
Amp.
Low-Pass
Filter
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