- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19396 > ADSP-21479KBCZ-2A (Analog Devices Inc)IC DSP SHARC 266MHZ LP 196CSPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-21479KBCZ-2A |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 196CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 266MHz |
| 非易失內(nèi)存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSPBGA（12x12） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)
Rev. A
|
Page 15 of 72
|
September 2011
SDRAS
O/T (ipu)
High-Z/
Driven High
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (ipu)
High-Z/
Driven High
SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction
with other SDRAM command pins, defines the operation for the SDRAM to
perform.
SDWE
O/T (ipu)
High-Z/
Driven High
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDCKE
O/T (ipu)
High-Z/
Driven High
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (ipu)
High-Z/
Driven High
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-
SDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM
accesses.
SDDQM
O/T (ipu)
High-Z/
Driven High
DQM Data Mask. SDRAM input mask signal for write accesses and output enable
signal for read accesses. Input data is masked when DQM is sampled high during
a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM
is sampled high during a read cycle. SDDQM is driven high from reset de-assertion
until SDRAM initialization completes. Afterwards, it is driven low irrespective of
whether any SDRAM accesses occur or not.
SDCLK
O/T (ipd)
High-Z/
Driving
SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers.
See Figure 47 on Page 61. For models in the 100-lead package, the SDRAM
interface should be disabled to avoid unnecessary power switching by setting the
DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC
Processor Hardware Reference.
DAI _P20–1
I/O/T (ipu)
High-Z
Digital Applications Interface. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip
audiocentric peripheral inputs or outputs connected to the pin and to the pin’s
output enable. The configuration registers of these peripherals then determines
the exact behavior of the pin. Any input or output signal present in the DAI SRU
may be routed to any of these pins.
DPI _P14–1
I/O/T (ipu)
High-Z
Digital Peripheral Interface. These pins provide the physical interface to the DPI
SRU. The DPI SRU configuration registers define the combination of on-chip
peripheral inputs or outputs connected to the pin and to the pin's output enable.
The configuration registers of these peripherals then determine the exact
behavior of the pin. Any input or output signal present in the DPI SRU may be
routed to any of these pins.
WDT_CLKIN
I
Watch Dog Timer Clock Input. This pin should be pulled low when not used.
WDT_CLKO
O
Watch Dog Resonator Pad Output.
WDTRSTO
O (ipu)
Watch Dog Timer Reset Out.
THD_P
I
Thermal Diode Anode. When not used, this pin can be left floating.
THD_M
O
Thermal Diode Cathode. When not used, this pin can be left floating.
Table 10. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMM36DRKF-S13 | CONN EDGECARD 72POS .156 EXTEND |
| GMM43DSEF-S13 | CONN EDGECARD 86POS .156 EXTEND |
| HWS150-3/A | PWR SUP IND 3.3V 30A SNG OUTPUT |
| HWS150-5/A | PWR SUP IND 5V 30A SNG OUTPUT |
| MAX6514UKP035+T | IC TEMP SWITCH SOT23-5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCP42100T-I/SL | 功能描述:數(shù)字電位計(jì) IC 256 Step SPI 100kOhm RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| MCP42100T-I/ST | 功能描述:數(shù)字電位計(jì) IC 256 Step SPI 100kOhm RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| MCP4231-103E/ML | 功能描述:數(shù)字電位計(jì) IC Digital Pot 128 step SPI dual Ch RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| MCP4231-103E/P | 功能描述:數(shù)字電位計(jì) IC Dual 7B V SPI POT RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| MCP4231-103-E/P | 功能描述:數(shù)字電位計(jì) IC Digital Pot, 128 steps, SPI, dual channel RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。