CLK_CFG1–0 I Core to CLKIN Ratio Control." />
參數(shù)資料
型號: ADSP-21479KBCZ-2A
廠商: Analog Devices Inc
文件頁數(shù): 9/72頁
文件大小: 0K
描述: IC DSP SHARC 266MHZ LP 196CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI,EBI/EMI,I²C,SPI,SPORT,UART/USART
時鐘速率: 266MHz
非易失內(nèi)存: ROM(4Mb)
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 196-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 196-CSPBGA(12x12)
包裝: 托盤
Rev. A
|
Page 17 of 72
|
September 2011
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the start up clock frequency.
Note that the operating frequency can be changed by programming the PLL
multiplier and divider in the PMCTL register at any time after the core comes out
of reset. The allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It
configures the processors to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the processors to use the external clock source
such as an external clock oscillator. CLKIN may not be halted, changed, or
operated below the specified frequency.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
RESETOUT/RUNRSTIN I/O (ipu)
Reset Out/Running Reset In. The default setting on this pin is reset out. This pin
also has a second function as RUNRSTIN which is enabled by setting bit 0 of the
RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
BOOT_CFG2–0
I
Boot Configuration Select. These pins select the boot mode for the processor.
The BOOT_CFG pins must be valid before RESET (hardware and software) is de-
asserted.
Note that the BOOT_CFG2 pin is not available on the 100-lead LQFP package.
Table 10. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.
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