參數(shù)資料
型號(hào)： ADSP-21479KBCZ-2A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 71/72頁(yè)
文件大?。?/td> 0K
描述： IC DSP SHARC 266MHZ LP 196CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（4Mb）
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（12x12）
包裝： 托盤
Rev. A
|
Page 8 of 72
|
September 2011
An AMI which communicates with SRAM, FLASH, and
other devices that meet the standard asynchronous SRAM
access protocol. The AMI supports 6M words of external
memory in bank 0 and 8M words of external memory in
bank 1, bank 2, and bank 3.
An SDRAM controller that supports a glueless interface
with any of the standard SDRAMs. The SDC supports 62M
words of external memory in bank 0, and 64M words of
external memory in bank 1, bank 2, and bank 3.
Arbitration logic to coordinate core and DMA transfers
between internal and external memory over the
external port.
External Port
The external port provides a high performance, glueless inter-
face to a wide variety of industry-standard memory devices. The
external port, available on the 196-ball CSP_BGA, may be used
to interface to synchronous and/or asynchronous memory
devices through the use of its separate internal memory control-
lers. The first is an SDRAM controller for connection of
industry-standard synchronous DRAM devices while the sec-
ond is an asynchronous memory controller intended to
interface to a variety of memory devices. Four memory select
pins enable up to four separate devices to coexist, supporting
any desired combination of synchronous and asynchronous
device types. Non-SDRAM external memory address space is
shown in Table 5.
SIMD Access to External Memory
The SDRAM controller supports SIMD access on the 64-bit
external port data bus (EPD) which allows access to the comple-
mentary registers on the PEy unit in the normal word space
(NW). This improves performance since there is no need to
explicitly load the complimentary registers (as in SISD mode).
VISA and ISA Access to External Memory
The SDRAM controller supports VISA code operation which
reduces the memory load since the VISA instructions are com-
pressed. Moreover, bus fetching is reduced because, in the best
case, one 48-bit fetch contains three valid instructions. Code
execution from the traditional ISA operation is also supported.
Note that code execution is only supported from bank 0 regard-
less of VISA/ISA. Table 6 shows the address ranges for
instruction fetch in each mode.
SDRAM Controller
The SDRAM controller, available on the ADSP-2147x in the
196-ball CSP_BGA package, provides an interface of up to four
separate banks of industry-standard SDRAM devices or
DIMMs, at speeds up to fSDCLK. Fully compliant with the
SDRAM standard, each bank has its own memory select line
(MS0–MS3), and can be configured to contain between
4M bytes and 256M bytes of memory. SDRAM external mem-
ory address space is shown in Table 7.
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. The
SDRAM and the AMI interface do not support 32-bit wide
devices.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF. For larger memory sys-
tems, the SDRAM controller external buffer timing should be
selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions as well as
32-bit data are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap.
Asynchronous Memory Controller
The asynchronous memory controller, available on the
ADSP-2147x in the 196-ball CSP_BGA package, provides a con-
figurable interface for up to four separate banks of memory or
I/O devices. Each bank can be independently programmed with
different timing parameters, enabling connection to a wide vari-
ety of memory devices including SRAM, flash, and EPROM, as
well as I/O devices that interface with standard memory control
lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3
occupy a 8M word window in the processor’s address space but,
if not fully populated, these windows are not made contiguous
by the memory controller logic.
Table 5. External Memory for Non-SDRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
6M
0x0020 0000–0x007F FFFF
Bank 1
8M
0x0400 0000–0x047F FFFF
Bank 2
8M
0x0800 0000–0x087F FFFF
Bank 3
8M
0x0C00 0000–0x0C7F FFFF
Table 6. External Bank 0 Instruction Fetch
Access Type
Size in
Words
Address Range
ISA (NW)
4M
0x0020 0000–0x005F FFFF
VISA (SW)
10M
0x0060 0000–0x00FF FFFF
Table 7. External Memory for SDRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
62M
0x0020 0000–0x03FF FFFF
Bank 1
64M
0x0400 0000–0x07FF FFFF
Bank 2
64M
0x0800 0000–0x0BFF FFFF
Bank 3
64M
0x0C00 0000–0x0FFF FFFF
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