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參數(shù)資料
| 型號(hào)： | ADSP-21479KBCZ-2A |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 196CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 266MHz |
| 非易失內(nèi)存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSPBGA（12x12） |
| 包裝： | 托盤 |
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Rev. A
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Page 11 of 72
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September 2011
Shift Register
The shift register can be used as a serial to parallel data con-
verter. The shift register module consists of an 18-stage serial
shift register, 18-bit latch, and three-state output buffers. The
shift register and latch have separate clocks. Data is shifted into
the serial shift register on the positive-going transitions of the
shift register serial clock (SR_SCLK) input. The data in each
flip-flop is transferred to the respective latch on a positive-going
transition of the shift register latch clock (SR_LAT) input.
The shift register’s signals can be configured as follows.
The SR_SCLK can come from any of the SPORT0–7 SCLK
outputs, PCGA/B clock, any of the DAI pins (1–8), and one
dedicated pin (SR_SCLK).
The SR_LAT can come from any of SPORT0–7 Frame sync
outputs, PCGA/B frame sync, any of the DAI pins (1–8),
and one dedicated pin (SR_LAT).
The SR_SDI input can from any of SPORT0–7 serial data
outputs, any of the DAI pins (1–8), and one dedicated pin
(SR_SDI).
Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must
come from same source except in the case of where SR_SCLK
comes from PCGA/B or SR_SCLK and SR_LAT come from
PCGA/B.
If SR_SCLK comes from PCGA/B, then SPORT0–7 generates
the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT
come from PCGA/B, then SPORT0–7 generates the SR_SDI
signal.
I/O PROCESSOR FEATURES
The I/O processor provides up to 65 channels of DMA as well as
an extensive set of peripherals.
DMA Controller
The DMA controller operates independently and invisibly to
the processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions. DMA
transfers can occur between the processor’s internal memory
and its serial ports, the SPI-compatible (serial peripheral inter-
face) ports, the IDP (input data port), the parallel data
acquisition port (PDAP) or the UART.
Up to 65 channels of DMA are available on the processors as
shown in Table 8.
Programs can be downloaded using DMA transfers. Other
DMA features include interrupt generation upon completion of
DMA transfers, and DMA chaining for automatic linked DMA
transfers.
Delay Line DMA
The processor provides delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and therefore to external memory) with limited core
interaction.
Scatter/Gather DMA
The processor provides scatter/gather DMA functionality. This
allows processor DMA reads/writes to/from noncontiguous
memory blocks.
FFT Accelerator
The FFT accelerator implements radix-2 complex/real input,
complex output FFTs with no core intervention. The FFT accel-
erator runs at the peripheral clock frequency.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
Watch Dog Timer (WDT)
The processors include a 32-bit watch dog timer that can be
used to implement a software watch dog function. A software
watch dog can improve system reliability by forcing the proces-
sor to a known state through generation of a system reset if the
timer expires before being reloaded by software. Software ini-
tializes the count value of the timer, and then enables the timer.
The WDT is used to supervise the stability of the system soft-
ware. When used in this way, software reloads the WDT in a
regular manner so that the downward counting timer never
expires. An expiring timer then indicates that system software
might be out of control.
The WDT resets both the core and the internal peripherals.
Software must be able to determine if the watch dog was the
source of the hardware reset by interrogating a status bit in the
watch dog timer control register.
Table 8. DMA Channels
Peripheral
DMA Channels
SPORTs
16
PDAP
8
SPI
2
UART
2
External Port
2
Accelerators
2
Memory-to-Memory
2
MediaLB1
31
1 Automotive models only.
Table 8. DMA Channels (Continued)
Peripheral
DMA Channels
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