
2005 Microchip Technology Inc.
DS21950B-page 11
MCP3551/3
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN FUNCTION TABLES
3.1
Voltage Reference (V
REF
)
The MCP3551/3 devices accept single-ended refer-
ence voltages from 0.1V to V
DD
. Since the converter
output noise is dominated by thermal noise, which is
independent of the reference voltage, the output noise
is not significantly improved by diminishing the refer-
ence voltage at the V
REF
input pin. A reduced voltage
reference will significantly improve the INL perfor-
mance (see Figure 2-4); the INL max error is propor-
tional to V
REF2
.
3.2
Analog Inputs (V
IN
+, V
IN
-)
The MCP3551/3 devices accept a fully differential ana-
log input voltage to be connected on the V
IN
+ and V
IN
-
input pins. The differential voltage that is converted is
defined by V
IN
= V
IN
+ - V
IN
-. The differential voltage
range specified for ensured accuracy is from -V
REF
to
+V
REF
. However, the converter will still output valid and
usable codes with the inputs overranged by up to 12%
(see
Section 5.0 “Serial Interface”
) at room
temperature. This overrange is clearly specified by two
overload bits in the output code.
The absolute voltage range on these input pins extends
from V
SS
- 0.3V to V
DD
+ 0.3V. Any voltage above or
below this range will create leakage currents through
the Electrostatic Discharge (ESD) diodes. This current
will increase exponentially, degrading the accuracy and
noise performance of the device. The common mode of
the analog inputs should be chosen such that both the
differential analog input range and the absolute voltage
range on each pin are within the specified operating
range defined in
Section 1.0 “Electrical Characteris-
tics”
.
3.3
Supply Voltage (V
DD
, V
SS
)
V
DD
is the power supply pin for the analog and digital
circuitry within the MCP3551/3. This pin requires an
appropriate bypass capacitor of 0.1 μF. The voltage on
this pin should be maintained in the 2.7V to 5.5V range
for specified operation. V
SS
is the ground pin and the
current return path for both analog and digital circuitry
of the MCP3551/3. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane of the Printed Circuit Board
(PCB).
3.4
Serial Clock (SCK)
SCK synchronizes data communication with the
device. The device operates in both SPI mode 1,1
and SPI mode 0,0. Data is shifted out of the device on
the falling edge of SCK. Data is latched in on the rising
edge of SCK. During CS high times, the SCK pin can
idle either high or low.
3.5
Data Output (SDO/RDY)
SDO/RDY is the output data pin for the device. Once a
conversion is complete, this pin will go active-low,
acting as a ready flag. Subsequent falling clock edges
will then place the 24-bit data word (two overflow bits
and 22 bits of data, see
Section 5.0 “Serial Inter-
face”
) on the SPI bus through the SDO pin. Data is
clocked out on the falling edge of SCK.
3.6
Chip Select (CS)
CS gates all communication to the device and can be
used to select multiple devices that share the same
SCK and SDO/RDY pins. This pin is also used to
control the internal conversions, which begin on the
falling edge of CS. Raising CS before the first internal
conversion is complete places the device in Single
Conversion mode. Leaving CS low will place the
device in Continuous Conversion mode (i.e., additional
internal conversions will automatically occur). CS may
be tied permanently low for two-wire Continuous
Conversion mode operation. SDO/RDY enters a
high-impedance state with CS high.
Pin No.
Symbol
I/O/P
Function
1
2
3
4
5
6
7
8
V
REF
V
IN
+
V
IN
-
V
SS
SCK
I
I
I
Reference Voltage Analog Input Pin
Non-inverting Analog Input Pin
Inverting Analog Input Pin
Ground Pin
Serial Clock Digital Input Pin
Data/Ready Digital Output Pin
Chip Select Digital Input Pin
Positive Supply Voltage Pin
P
I
O
I
P
SDO/RDY
CS
V
DD
Type Identification: I = Input; O = Output; P = Power