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參數(shù)資料
型號(hào)： MCP3201-CI/MS
廠商： Microchip Technology
文件頁數(shù)： 34/40頁
文件大小： 0K
描述： IC ADC 12BIT 2.7V 1CH SPI 8MSOP
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極
MCP3201
DS21290F-page 4
1998-2011 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
High Level Output Voltage
VOH
4.1
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
——
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
A
VOUT = VSS or VDD
Pin Capacitance
(all inputs/outputs)
CIN, COUT
—
10
pF
VDD = 5.0V (Note 1)
TA = +25°C, f = 1 MHz
Timing Parameters:
Clock Frequency
fCLK
—
1.6
0.8
MHz
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Clock High Time
tHI
312
—
ns
Clock Low Time
tLO
312
—
ns
CS Fall To First Rising CLK Edge
tSUCS
100
—
ns
CLK Fall To Output Data Valid
tDO
—
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
—
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
—
100
ns
See Test Circuits, Figure 1-2
CS Disable Time
tCSH
625
—
ns
D
OUT Rise Time
tR
—
100
ns
See Test Circuits, Figure 1-2
D
OUT Fall Time
tF
—
100
ns
See Test Circuits, Figure 1-2
Power Requirements:
Operating Voltage
VDD
2.7
—
5.5
V
Operating Current
IDD
—
300
210
400
—
A
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
—0.5
2
A
CS = VDD = 5.0V
Electrical Specifications:
Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP
JA
—211
—
°C/W
Thermal Resistance, 8L-PDIP
JA
—89.5
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
149.5
—
°C/W
Thermal Resistance, 8L-TSSOP
JA
—139
—
°C/W
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and
fCLK = 16*fSAMPLE, unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graph that relates linearity performance to VREF level.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.
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