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| 型號： | MCP3201-CI/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2.7V 1CH SPI 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
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1998-2011 Microchip Technology Inc.
DS21290F-page 19
MCP3201
5.0
SERIAL COMMUNICATIONS
Communication with the device is done using a
standard SPI-compatible serial interface. Initiating
communication with the MCP3201 device begins with
the CS going low. If the device was powered up with the
CS pin low, it must be brought high and back low to
initiate communication. The device will begin to sample
the analog input on the first rising edge after CS goes
low. The sample period will end in the falling edge of the
second clock, at which time the device will output a low
null bit. The next 12 clocks will output the result of the
conversion with MSB first, as shown in Figure 5-1. Data
is always output from the device on the falling edge of
the clock. If all 12 data bits have been transmitted and
the device continues to receive clocks while the CS is
held low, the device will output the conversion result
LSB first, as shown in Figure 5-2. If more clocks are
provided to the device while CS is still low (after the
LSB first data has been transmitted), the device will
clock out zeros indefinitely.
FIGURE 5-1:
Communication with MCP3201 device using MSB first Format.
FIGURE 5-2:
Communication with MCP3201 device using LSB first Format.
CS
CLK
D
OUT
tCYC
POWER
DOWN
TSUCS
TSAMPLE
tCONV
tDATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure 5-2 below.
** tDATA: during this time, the bias current and the comparator power-down and the reference input becomes a high-impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
TCSH
NULL
BIT B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0*
HI-Z
B11 B10 B9
B8
NULL
BIT
CS
CLK
D
OUT
tCYC
POWER DOWN
tSUCS
tSAMPLE
tCONV
tDATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power-down and the reference input becomes a high-impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
tCSH
NULL
BIT B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
HI-Z
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11*
HI-Z
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