參數(shù)資料
型號(hào)： MCP23S09T-E/MG
廠商： Microchip Technology
文件頁數(shù)： 20/50頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER SPI 8B 16QFN
標(biāo)準(zhǔn)包裝： 3,300
接口： SPI
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時(shí)鐘： 10MHz
電源電壓： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-QFN-EP（3x3）
包裝： 帶卷 (TR)
2009 Microchip Technology Inc.
DS22121B-page 27
MCP23009/MCP23S09
1.7
Interrupt Logic
If enabled, the MCP23X09 activates the INT interrupt
output when one of the port pins changes state or when
a pin does not match the pre-configured default. Each
pin is individually configurable as follows:
Enable/disable interrupt via GPINTEN
Can interrupt on either pin change or change from
default as configured in DEFVAL
Both conditions are referred to as Interrupt on Change
(IOC).
The Interrupt Control Module uses the following
registers/bits:
GPINTEN - Interrupt enable register
INTCON - Controls the source for the IOC
DEFVAL - Contains the register default for IOC
operation
IOCON (ODR and INTPOL) - configures the INT
pin as push-pull, open-drain, and active level
(high or low).
1.7.1
IOC FROM PIN CHANGE
If enabled, the MCP23X09 will generate an interrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC enabled
pins will be compared. See GPINTEN and INTCON
registers.
1.7.2
IOC FROM REGISTER DEFAULT
If enabled, the MCP23X09 will generate an interrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins will be compared. See
GPINTEN, INTCON, and DEFVAL registers.
1.7.3
INTERRUPT OPERATION
The INT interrupt output can be configured as “active
low”, “active high”, or “open-drain” via the IOCON
register.
Only those pins that are configured as an input (IODIR
register)
with
interrupt-on-change
(IOC)
enabled
(GPINTEN register) can cause an interrupt. Pins
configured as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC will generate an internal device interrupt and
the device will capture the value of the port and copy it
into INTCAP.
The first interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
interrupt conditions on the port will not cause an
interrupt to occur as long as the interrupt is not cleared
by a read of INTCAP or GPIO.
1.7.4
CLEARING INTERRUPTS
The interrupt will remain active until the INTCAP or
GPIO register is read (depending on IOCON.INTCC).
Writing to these registers will not affect the interrupt.
The interrupt condition will be cleared after the LSb of
the data is clocked out during a Read operation of
GPIO or INTCAP (depending on IOCON.INTCC).
Note:
Assuming IOCON.INTCC = 0 (INT cleared
on GPIO read): The value in INTCAP can
be lost if GPIO is read before INTCAP
while another IOC is pending. After read-
ing GPIO, the interrupt will clear and then
set due to the pending IOC, causing the
INTCAP register to update.
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