參數(shù)資料
型號(hào)： MCM63R836
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： MCM63R836
中文描述： MCM63R836
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 363K
代理商： MCM63R836
MCM63R836
MCM63R918
9
MOTOROLA FAST SRAM
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address setup time is shown as a minimum since
the system must supply at least that much time. On the
other hand, responses from the memory are specified
from the device point of view. Thus, the access time is
shown as a maximum since the device never provides
data later than that time.
TIMING LIMITS
DEVICE
UNDER
TEST
ZQ
50
50
0.75 V
VDDQ/2
Vref
250
Figure 1. Test Loads
50
50
0.75 V
0.75 V
50
50
5 pF
5 pF
16.7
DQ
16.7
16.7
0.75 V
a. Test Load
b. Test Load
AC INPUT CHARACTERISTICS
(See Note 1)
Parameter
Symbol
Min
Max
Notes
AC Input Logic High (See Figure 4)
VIH (ac)
Vref + 200 mV
—
AC Input Logic Low (See Figures 2 and 4)
VIL (ac)
—
Vref – 200 mV
2
Input Reference Peak to Peak ac Voltage
Vref (ac)
—
5% Vref (dc)
3
Clock Input Differential Voltage
Vdif (ac)
400 mV
VDDQ + 500 mV
4
NOTES:
1. Inputs may overshoot to 3.3 V for up to 35% tKHKH or 1.0 ns, whichever is smaller, and 3.8 V instantaneous peak overshoot. See Figure 2.
2. Inputs may undershoot to VSS – 1.0 V for up to 35% tKHKH or 1.0 ns, whichever is smaller, and VSS – 1.5 V instantaneous peak undershoot.
See Figure 2.
3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
4. Minimum instantaneous differential input voltage required for differential input clock operation.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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