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參數(shù)資料
| 型號： | MCM63R836 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | MCM63R836 |
| 中文描述： | MCM63R836 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 363K |
| 代理商： | MCM63R836 |
MCM63R836
MCM63R918
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(2.375 V
≤
VDD
≤
3.6 V, 0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Max
–3.0
Max
–3.3
Max
–3.7
Max
–4.0
Max
Unit
Notes
Core Power Supply Voltage
VDD
VDDQ
IDD1
2.375
—
—
—
—
3.6
V
Output Driver Supply Voltage
1.4
—
—
—
—
2.0
V
AC Supply Current
(Device Selected,
All Outputs Open, Freq = Max,
VDD = Max, VDDQ = Max). Includes
Supply Currents for VDD.
x36
x18
—
—
500
450
480
430
460
410
440
390
500
450
mA
5
Quiescent Active Power Supply Current
(Device Selected, All Outputs Open,
Freq = 0, VDD = Max, VDDQ = Max).
Includes Supply Currents for VDD.
Active Standby Power Supply Current
(Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max).
IDD2
—
175
175
175
175
175
mA
6
ISB1
—
200
195
190
185
200
mA
7
CMOS Standby Supply Current (Device
Deselected, Freq = 0, VDD = Max,
VDDQ = Max, All Inputs Static at
CMOS Levels).
ISB2
—
175
175
175
175
175
mA
6, 7
Sleep Mode Current (ZZ = VIH,
VDD = Max, VDDQ = Max)
IZZ
—
50
50
50
50
50
mA
6, 7
Input Reference DC Voltage
Vref (dc)
0.6
—
—
—
—
1.3
V
8
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. All inputs are zero.
6. CMOS levels for I/Os are VIC
≤
VSS + 0.2 V or
≥
VDDQ – 0.2 V.
7. Device deselected as defined by the Truth Table.
8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
VIL (dc)
Ilkg(I)
Vin (dc)
VDIF (dc)
VCM (dc)
VX
Vref + 0.1
–0.3
VDDQ + 0.3
Vref – 0.1
±
5
V
DC Input Logic Low
V
Input Leakage Current
—
μ
A
1, 2
Clock Input Signal Voltage
–0.3
2.5
V
Clock Input Differential Voltage
0.2
2.5
V
3
Clock Input Common Mode Voltage Range (See Figure 2)
0.60
1.3
V
4
Clock Input Crossing Point Voltage Range (See Figure 2)
0.60
1.3
V
NOTES:
1. 0 V
≤
Vin
≤
VDDQ for all pins.
2. Measured at Vref = 0.75 V.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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