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參數(shù)資料
| 型號： | MCIMX31LDVKN5D |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-457 |
| 文件頁數(shù)： | 81/118頁 |
| 文件大?。?/td> | 1083K |
| 代理商： | MCIMX31LDVKN5D |
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Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
65
4.3.15.4.2
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical
4.3.15.5
Asynchronous Interfaces
4.3.15.5.1
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) of by the HBURST signal
(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system
68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when
transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD
signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during
the whole burst.
2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 51,
DISPB_D#_WR and DISPB_D#_RD signals.
Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the
HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to
different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX31LDVKN5DR2 | 功能描述:處理器 - 專門應用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX31LDVMN5D | 功能描述:處理器 - 專門應用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX31LDVMN5DR2 | 功能描述:處理器 - 專門應用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX31LITEKIT | 制造商:Freescale Semiconductor 功能描述:I.MX31 LITE KIT 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述:EVAL BOARD FOR 1.MX31 MPV 制造商:Freescale Semiconductor 功能描述:MX31 Lite Kit: High-performance application development kit, Silicon Manufacture |
| MCIMX31LITEKITC | 功能描述:開發(fā)板和工具包 - ARM I.MX31 LITE KIT RoHS:否 制造商:Arduino 產品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
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