參數(shù)資料
型號(hào): MCIMX27VJP4A
廠商: Freescale Semiconductor
文件頁數(shù): 97/152頁
文件大小: 0K
描述: MPU IMX27 404-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX27
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲(chǔ)器類型: ROMless
RAM 容量: 45K x 8
電壓 - 電源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振蕩器型: 外部
工作溫度: -20°C ~ 85°C
封裝/外殼: 404-LFBGA
包裝: 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
49
Electrical Characteristics
Figure 8. ATA interface Signals Timing Diagram
4.2.4
Digital Audio Mux (AUDMUX)
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI, SAP) and external serial interfaces (audio and voice codecs). The AC timing
of AUDMUX external pins is hence governed by SSI and SAP modules. Please refer to their respective
electrical specifications.
4.2.5
CMOS Sensor Interface (CSI)
This section describes the electrical information (AC timing) of the CSI.
4.2.5.1
Gated Clock Mode Timing
VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on
VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC
is high. Figure 9 and Figure 10 depict the gated clock mode timings of CSI, and Table 21 lists the timing
parameters.
SI3
Host interface signal capacitance at the host
connector
Chost
—20
pF
Note: SRISE and SFALL meets this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value.
Table 20. AC Characteristics of All Interface Signals (continued)
ID
Parameter
Symbol
Min
Max
Unit
ATA Interface Signals
SI1
SI2
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