參數(shù)資料
型號: MCIMX27MJP4A
廠商: Freescale Semiconductor
文件頁數(shù): 96/152頁
文件大小: 0K
描述: MPU IMX27 473-MAPBGA
產品培訓模塊: i.MX27 Multimedia Application Processor
標準包裝: 84
系列: i.MX27
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 45K x 8
電壓 - 電源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 473-LFBGA
包裝: 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
48
Freescale Semiconductor
Electrical Characteristics
Figure 7. Read Sequence Timing Diagram
4.2.3
ATA Electrical Specifications
This section describes the electrical information of the Parallel ATA module compliant with ATA/ATAPI-6
specification.
NOTE
The parallel ATA module is not available on the i.MX27L
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MB/s. Parallel ATA
module interface consist of a total of 29 pins, Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Below defines the AC characteristics of all the interface signals on all data transfer modes.
4.2.3.1
General Timing Requirements
These are the general timing requirements for the ATA interface signals.
Table 19. Write 1/Read Timing Parameters
ID
Parameter
Symbol
Min
Typical
Max
Units
OW7
Write 1/Read Low Time
tLOW1
15
s
OW8
Transmission Time Slot
tSLOT
60
117
120
s
OW9
Release Time
tRELEASE
15
45
s
Table 20. AC Characteristics of All Interface Signals
ID
Parameter
Symbol
Min
Max
Unit
SI1
Rising edge slew rate for any signal on ATA
interface (see note)
Srise
1.25
V/ns
SI2
Falling edge slew rate for any signal on ATA
interface (see note)
Sfall
1.25
V/ns
OW7
OW8
OW9
One-Wire bus
(BATT_LINE)
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