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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MCIMX27MJP4A |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 110/152闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | MPU IMX27 473-MAPBGA |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | i.MX27 Multimedia Application Processor |
| 妯欐簴鍖呰锛� | 84 |
| 绯诲垪锛� | i.MX27 |
| 鏍稿績铏曠悊鍣細 | ARM9 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 400MHz |
| 閫ｉ€氭€э細 | 1 绶�锛孋AN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孧MC锛屾櫤鑳藉崱锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孡CD锛孭OR锛孭WM锛學DT |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| RAM 瀹归噺锛� | 45K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.38 V ~ 1.52 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 473-LFBGA |
| 鍖呰锛� | 鎵樼洡 |
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i.MX27 and i.MX27L Data Sheet, Rev. 1.8
60
Freescale Semiconductor
Electrical Characteristics
4.3.3
Inter IC Communication (I2C)
This section describes the electrical information of the I2C module.
4.3.3.1
I2C Module Timing
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 21 shows the timing of the
Figure 21. I2C Bus Timing Diagram
Table 28. MII Serial Management Channel Timing Parameters
ID
Parameter
Min
Max
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
0
鈥�
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
鈥�
5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
鈥�
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
鈥�
ns
M14
FEC_MDC pulse width high
40% 60%
FEC_MDC period
M15
FEC_MDC pulse width low
40% 60%
FEC_MDC period
Table 29. I2C Module Timing Parameters
ID
Parameter
1.8 V +/鈥�0.10 V
3.0 V +/鈥�0.30 V
Unit
Min
Max
Min
Max
鈥�
SCL Clock Frequency
0
100
0
100
kHz
IC1
Hold time (repeated) START Condition
114.8
鈥�
111.1
鈥�
ns
IC2
Data Hold Time
0
69.7
0
72.3
ns
IC3
Data Setup Time
3.1
鈥�
1.76
鈥�
ns
IC4
HIGH period of the SCL clock
69.7
鈥�
68.3
鈥�
ns
IC5
LOW period of the SCL clock
336.4
鈥�
335.1
鈥�
ns
IC6
Setup Time for STOP condition
110.5
鈥�
111.1
鈥�
ns
IC1
IC6
SDA
SCL
IC3
IC2
IC5
IC4
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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