The i.MX27/MX27L proces" />
參數(shù)資料
型號： MCIMX27LMOP4A
廠商： Freescale Semiconductor
文件頁數(shù)： 82/152頁
文件大?。?/td> 0K
描述： IC MPU I.MX27 IN 19X19 473MAPBGA
標準包裝： 84
系列： i.MX27
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 45K x 8
電壓 - 電源 (Vcc/Vdd)： 1.38 V ~ 1.52 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 473-LFBGA
包裝： 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
35
Signal Descriptions
3.1
Power-Up Sequence
The i.MX27/MX27L processor consists of three major sets for power supply voltage named QVDD (core
logic supply), FUSEVDD (analog supply for FUSEBOX), and NVDD,VDDA (IO supply). The External
Voltage Regulators and power-on devices must provide the applications processor with a specific sequence
of power and resets to ensure proper operation.
It is important that the applications processor power supplies be powered-up in a certain order to avoid
unintentional fuse blown. QVDD should be powered up before FUSEVDD. The recommended order is:
1. QVDD(1.5 V)
2. FUSEVDD (1.8 V), NVDD (1.8/2.775 V), and Analog Supplies (2.775 V). See Table 3 for signal
descriptions.
or
1. Q
VDD (1.5 V), NVDD (1.8/2.775 V), and Analog Supplies (2.775 V). See Table 3 for signal
descriptions.
2. FUSEVDD (1.8 V).
3.2
EMI Pins Multiplexing
This section discusses the multiplexing of EMI signals. The EMI signals’ multiplexing is done inside the
EMI. Table 4 lists the i.MX27 pin names, pad types, and the memory devices’ equivalent pin names.
Note: Both 1-Wire and Fast Ethernet Controller signals are multiplexed with other signals. As a result these signal names do not
appear in this list. The signals are listed below with the named signal that they are multiplexed.
1-Wire Signals:
The 1-Wire input and output signal is multiplexed with JTAG RTCK pad, PE16.
Fast Ethernet Controller (FEC) Signals on the i.MX27. The ATA module does not exist on the i.MX27L:
FEC_TX_EN: Transmit enable signal, through GPIO multiplexed with ATA_DATA15 pad; PF23
FEC_TX_ER: Transmit Data Error; through GPIO multiplexed with ATA_DATA14 pad; PD16
FEC_COL: Collision signal; through GPIO multiplexed with ATA_DATA13 pad; PD15
FEC_RX_CLK: Receive Clock signal; through GPIO multiplexed with ATA_DATA12 pad; PD14
FEC_RX_DV: Receive data Valid signal; through GPIO multiplexed with ATA_DATA11 pad; PD13
FEC_RXD0: Receive Data0; through GPIO multiplexed with ATA_DATA10 pad; PD12
FEC_TX_CLK: Transmit Clock signal; through GPIO multiplexed with ATA_DATA9 pad; PD11
FEC_CRS: Carrier Sense enable; through GPIO multiplexed with ATA_DATA8 pad; PD10
FEC_MDC: Management Data Clock; through GPIO multiplexed with ATA_DATA7 pad; PD9
FEC_MDIO: Management Data Input/Output, multiplexed with ATA_DATA6 pad; PD8
FEC_RXD3–1: Receive Data; through GPIO multiplexed with ATA_DATA5–3 pad; PD7–5
FEC_RX_ER: Receive Data Error; through GPIO multiplexed with ATA_DATA2 pad; PD4
FEC_TXD3–2: Transmit Data; through GPIO multiplexed with ATA_DATA1–0; pad; PD3–2
FEC_TXD1: Transmit Data; through GPIO multiplexed with SD3_CLK pad; PD1
FEC_TXD0: Transmit Data; through GPIO multiplexed with SD3_CMD pad; PD0
Note: The Rest ATA signals are multiplexed with PCMCIA Pads.
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Pad Name
Function/Notes
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