參數(shù)資料
型號： MCIMX27LMOP4A
廠商： Freescale Semiconductor
文件頁數(shù)： 105/152頁
文件大?。?/td> 0K
描述： IC MPU I.MX27 IN 19X19 473MAPBGA
標(biāo)準(zhǔn)包裝： 84
系列： i.MX27
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 45K x 8
電壓 - 電源 (Vcc/Vdd)： 1.38 V ~ 1.52 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 473-LFBGA
包裝： 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
56
Freescale Semiconductor
Electrical Characteristics
4.3.1
Direct Memory Access Controller (DMAC)
After assertion of External DMA Request the DMA burst will start when the corresponding DMA channel
becomes the current highest priority channel. The External DMA Request should be kept asserted until it
is serviced by the DMAC. One External request will initiate at least one DMA burst.
The output External Grant signal from the DMAC is an active-low signal. This signal will be asserted
during the time when a DMA burst is ongoing for an External DMA Request, when the following
conditions are true:
The DMA channel for which the DMA burst is ongoing has requested source as external DMA
Request (as per RSSR settings).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
Once the grant is asserted the External DMA Request will not be sampled until completion of the DMA
burst. The priority of the external request will become low, for the next consecutive burst, if another DMA
request signal is asserted.
The waveforms are shown for the worst case—that is, smallest burst (1 byte read/write). Minimum and
maximum timings for the External request and External grant signal are present in the data sheet.
Figure 15 shows the minimum time for which the External Grant signal remains asserted if External DMA
request is de-asserted immediately after sensing grant signal active.
Figure 15. Assertion of DMA External Grant Signal
Figure 16 shows the safe maximum time for which External DMA request can be kept asserted, after
sensing grant signal active such that a new burst is not initiated.
Figure 16. Timing Diagram of Safe Maximums for External Request De-Assertion
Ext_DMAReq
Ext_DMAGrant
tmin_assert
Ext_DMAReq
Data read from
External device
Data written to
External device
Ext_DMAGrant
tmax_write
tmax_read
tmax_req_assert
NOTE: Assuming worst case that the data is read/written from/to external device as per the above waveform.
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