參數(shù)資料
型號: MCIMX27LMOP4A
廠商: Freescale Semiconductor
文件頁數(shù): 140/152頁
文件大?。?/td> 0K
描述: IC MPU I.MX27 IN 19X19 473MAPBGA
標準包裝: 84
系列: i.MX27
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 45K x 8
電壓 - 電源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 473-LFBGA
包裝: 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
88
Freescale Semiconductor
Electrical Characteristics
NOTE
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is the
same as that of Tx Data, for example, during the AC97 mode of operation.
4.3.11.3
SSI Transmitter Timing with External Clock
Figure 49 and Figure 50 show the SSI transmitter timing with external clock, and Table 48 lists the timing
parameters.
Figure 49. SSI Transmitter with External Clock Timing Diagram
SS49
Oversampling clock rise time
3
ns
SS50
Oversampling clock low period
6
ns
SS51
Oversampling clock fall time
3
ns
Table 47. SSI Receiver with Internal Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
SS45
SS33
SS24
SS26
SS25
SS23
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
AD1_TXD
AD1_RXD
Note: SRXD Input in Synchronous mode only
SS31
SS29
SS27
SS22
SS44
SS39
SS38
SS37
SS46
(Input)
(Output)
(Input)
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