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參數(shù)資料
| 型號： | MCF5480 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | MCF548x ColdFire㈢ Microprocessor |
| 中文描述： | MCF548x微處理器的ColdFire㈢ |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 403K |
| 代理商： | MCF5480 |
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Hardware Design Considerations
MCF548x ColdFire
Microprocessor, Rev. 4
Freescale Semiconductor
7
Figure 3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD V
DD
and EV
DD
is non-critical during power-up and power-down sequences. SD V
DD
(2.5V or
3.3V) and EV
DD
are specified relative to IV
DD
.
4.2.1
Power Up Sequence
If EV
DD
/SD V
DD
are powered up with the IV
DD
at 0V, the sense circuits in the I/O pads cause all pad output drivers connected
to the EV
DD
/SD V
DD
to be in a high impedance state. There is no limit to how long after EV
DD
/SD V
DD
powers up before IV
DD
must power up. IV
DD
should not lead the EV
DD
, SD V
DD
, or PLL V
DD
by more than 0.4V during power ramp up or there is
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond
to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1.
Use 1 microsecond or slower rise time for all supplies.
2.
IV
DD
/PLL V
DD
and EV
DD
/SD V
DD
should track up to 0.9V, then separate for the completion of ramps with EV
DD
/SD
V
DD
going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
4.2.2
Power Down Sequence
If IV
DD
PLL V
DD
are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IV
DD
and PLL V
DD
power down before EV
DD
or SD V
DD
must power down. IV
DD
should
not lag EV
DD
, SD V
DD
, or PLL V
DD
going low by more than 0.4V during power down or there is undesired high current in the
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
Drop IV
DD
/PLL V
DD
to 0V
2.
Drop EV
DD
/SD V
DD
supplies
EV
DD
, SD V
DD
(3.3V)
SD V
DD
(2.5V)
IV
DD
, PLL V
DD
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
NOTES:
1.
IVDD should not exceed EVDD or SD VDD by more than 0.4V
at any time, including power-up.
Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to
0.9V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (EVDD, SD VDD,
IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.
Use 1 microsecond or slower rise time for all supplies.
2.
3.
4.
D
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| MCF5481 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF5481CVR166 | 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5481CZP166 | 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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