參數(shù)資料
型號: MCF54418CMJ250
廠商: Freescale Semiconductor
文件頁數(shù): 51/61頁
文件大小: 0K
描述: IC MCU 32BIT 256MAPBGA
標(biāo)準(zhǔn)包裝: 450
系列: MCF5441x
核心處理器: Coldfire V4
芯體尺寸: 32-位
速度: 250MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,智能卡,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 87
程序存儲器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.14 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
55
Figure 36. RGPIO timing
4.29
JTAG and boundary scan timing specifications
All JTAG signals use pad type pad_msr except for TCLK which use pad type pad_fsr. The following timing specifications
assume a pad slew rate setting of 11 and a load of 50 pF.1
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 40. JTAG and boundary scan timing
Num
Characteristics1
1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
Min
Max
Unit
J1
TCLK frequency of operation
DC
25
MHz
J2
TCLK cycle period
40
ns
J3
TCLK clock pulse width
20
ns
J4
TCLK rise and fall times
3
ns
J5
Boundary scan input data setup time to TCLK rise
4
ns
J6
Boundary scan input data hold time after TCLK rise
20
ns
J7
TCLK low to boundary scan output data valid
13
ns
J8
TCLK low to boundary scan output high-Z
13
ns
J9
TMS, TDI input data setup time to TCLK rise
4
ns
J10
TMS, TDI input data hold time after TCLK rise
10
ns
J11
TCLK low to TDO data valid
12
ns
J12
TCLK low to TDO high-Z
0
ns
J13
TRST assert time
32
ns
J14
TRST setup time (negation) to TCLK high
8
ns
RG1
PST_CLK
RGPIO Outputs
RGPIO Inputs
RG2
RG3
RG4
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