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    參數(shù)資料
    型號(hào): MCF54418CMJ250
    廠商: Freescale Semiconductor
    文件頁數(shù): 41/61頁
    文件大?。?/td> 0K
    描述: IC MCU 32BIT 256MAPBGA
    標(biāo)準(zhǔn)包裝: 450
    系列: MCF5441x
    核心處理器: Coldfire V4
    芯體尺寸: 32-位
    速度: 250MHz
    連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,智能卡,SPI,SSI,UART/USART,USB,USB OTG
    外圍設(shè)備: DMA,PWM,WDT
    輸入/輸出數(shù): 87
    程序存儲(chǔ)器類型: ROMless
    RAM 容量: 64K x 8
    電壓 - 電源 (Vcc/Vdd): 1.14 V ~ 1.32 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 256-LBGA
    包裝: 托盤
    MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
    Electrical characteristics
    Freescale Semiconductor
    46
    4.20
    mcPWM timing specifications
    4.21
    I2C timing specifications
    Table 29 lists specifications for the I2C input timing parameters shown in Figure 27.
    Table 30 lists specifications for the I2C output timing parameters shown in Figure 27.
    Integral non-linearity (497 to 3599)
    INL
    ±8.0
    lsb
    Differential non-linearity (497 to 3599)
    DNL
    ±0.5
    lsb
    Gain error (497 to 3599)
    EGAIN
    ±0.26
    %
    Effective number of bits
    ENOB
    9
    bits
    DAC power-up time
    tDAPU
    11
    us
    Output load resistance
    RL
    3K
    Ohm
    Output load capacitance
    CL
    400
    pF
    Power supply ripple rejection
    PSRR
    60
    dB
    1
    All measurements were made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
    Table 28. mcPWM timing
    Num
    Characteristic
    Min
    Max
    Unit
    G1
    FB_CLK high to output valid
    7
    ns
    G2
    FB_CLK high to output invalid
    1
    ns
    G3
    Input valid to FB_CLK high
    3
    ns
    G4
    FB_CLK high to input invalid
    1
    ns
    Table 29. I2C input timing specifications between SCL and SDA
    Num
    Characteristic
    Min
    Max
    Units
    I1
    Start condition hold time
    2
    1/fSYS
    I2
    Clock low period
    8
    1/fSYS
    I3
    I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
    1
    ms
    I4
    Data hold time
    0
    ns
    I5
    I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)
    1
    ms
    I6
    Clock high time
    4
    1/fSYS
    I7
    Data setup time
    0
    ns
    I8
    Start condition setup time (for repeated start condition only)
    2
    1/fSYS
    I9
    Stop condition setup time
    2
    1/fSYS
    Table 27. DAC parameters1 (continued)
    Characteristic
    Name
    Min
    Typical
    Max
    Unit
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