參數(shù)資料
型號(hào)： MCF54418CMJ250
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 22/61頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5441x
核心處理器： Coldfire V4
芯體尺寸： 32-位
速度： 250MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，智能卡，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 87
程序存儲(chǔ)器類型： ROMless
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.14 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
29
Figure 10. RESET and configuration override timing
4.10
FlexBus timing specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a
reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the FlexBus output clock
(FB_CLK). All other timing relationships can be derived from these values.
All FlexBus signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load
of 50 pF.1
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 16. FlexBus timing specifications
Num
Characteristic
Min
Max
Unit
Notes
Frequency of operation
—
62.5
MHz
FB1
Clock period
16
—
ns
FB2
Output valid
—
6.0
ns
1
1 Specification is valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn,
and FB_TSIZ[1:0].
FB3
Output hold
0.5
—
ns
FB4
Input setup
5.5
—
ns
2
2 Specification is valid for all FB_AD[31:0] and FB_TA.
FB5
Input hold
0
—
ns
R1
R2
FB_CLK
RESET
RSTOUT
R3
R4
R8
R7
R6
R5
R4
BOOTMOD[1:0]
R9
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