參數(shù)資料
型號(hào): MCF54418CMJ250
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA256
封裝: 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256
文件頁(yè)數(shù): 42/60頁(yè)
文件大?。?/td> 1107K
代理商: MCF54418CMJ250
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
47
4.22.1
Receive signal timing specifications
The following timing specs meet the requirements for MII and RMII interfaces for a range of transceiver devices.
Figure 28. MII/RMII receive signal timing diagram
4.22.2
Transmit signal timing specifications
Table 31. Receive signal timing
Num
Characteristic
MII mode
RMII mode
Unit
Min
Max
Min
Max
RXCLK frequency
25
50
MHz
E1
RXD[n:0], RXDV, RXER to RXCLK setup1
1 In MII mode, n = 3; In RMII mode, n = 1
5—4—
ns
E2
RXCLK to RXD[n:0], RXDV, RXER hold1
5—2—
ns
E3
RXCLK pulse width high
35%
65%
35%
65%
RXCLK period
E4
RXCLK pulse width low
35%
65%
35%
65%
RXCLK period
Table 32. Transmit signal timing
Num
Characteristic
MII mode
RMII mode
Unit
Min
Max
Min
Max
TXCLK frequency
25
50
MHz
E5
TXCLK to TXD[n:0], TXEN, TXER invalid1
1 In MII mode, n = 3; In RMII mode, n = 1
4—5—
ns
E6
TXCLK to TXD[n:0], TXEN, TXER valid1
25
14
ns
E7
TXCLK pulse width high
35%
65%
35%
65%
tTXCLK
E8
TXCLK pulse width low
35%
65%
35%
65%
tTXCLK
Valid Data
RXCLK (MII) / EXTAL (RMII)
RXD[n:0]
RXDV,
RXER
E3
E4
E1
E2
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