參數(shù)資料
型號(hào)： MCF5372
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microprocessor Data Sheet
中文描述： 微處理器數(shù)據(jù)表
文件頁(yè)數(shù)： 25/42頁(yè)
文件大?。?/td> 787K
代理商： MCF5372
Preliminary Electrical Characteristics
MCF5373 ColdFire
Microprocessor Data Sheet, Rev. 0.3
Preliminary
Freescale Semiconductor
25
SD4
Pulse Width Low
t
SDCKH
0.45
0.55
SD_CLK
4
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
t
SDCHACV
—
0.5
×
SD_CLK
+ 1.0
ns
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
t
SDCHACI
2.0
—
ns
SD7
SD_SDR_DQS Output Valid
t
DQSOV
—
Self timed
ns
5
SD8
SD_DQS[3:0] input setup relative to SD_CLK
t
DQVSDCH
0.25
×
SD_CLK
0.40
×
SD_CLK
ns
6
SD9
SD_DQS[3:2] input hold relative to SD_CLK
t
DQISDCH
Does not apply. 0.5
×
SD_CLK fixed
width.
7
SD10
Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
t
DVSDCH
0.25
×
SD_CLK
—
ns
8
SD11
Data Input Hold relative to SD_CLK (reference only)
t
DISDCH
1.0
—
ns
SD12
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
t
SDCHDMV
—
0.75
×
SD_CLK
+ 0.5
ns
SD13
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
t
SDCHDMI
1.5
—
ns
NOTES:
1
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the
MCF5373 Reference Manual
for more information on setting the SDRAM clock rate.
2
SD_CLK is one SDRAM clock in (ns).
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
4
Pulse width high plus pulse width low cannot exceed min and max clock period.
5
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
6
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
7
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
8
Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup
spec is just provided as guidance.
Table 11. SDR Timing Specifications (continued)
Symbol
Characteristic
Symbol
Min
Max
Unit
Notes
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