MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Fr" />
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寤犲晢锛� Freescale Semiconductor
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灏佽/澶栨锛� 196-LBGA
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Electrical Characteristics
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
23
Figure 8. FlexBus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device鈥檚 SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 10. SDR Timing Specifications
Symbol
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation1
60
80
MHz
SD1
Clock Period2
tSDCK
12.5
16.67
ns
SD3
Pulse Width High3
tSDCKH
0.45
0.55
SD_CLK
SD4
Pulse Width Low4
tSDCKH
0.45
0.55
SD_CLK
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
tSDCHACV
鈥�
0.5
脳 SD_CLK
+1.0
ns
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
鈥�
ns
SD7
SD_SDR_DQS Output Valid5
tDQSOV
鈥�
Self timed
ns
SD8
SD_DQS[3:0] input setup relative to SD_CLK6
tDQVSDCH
0.25
脳
SD_CLK
0.40
脳 SD_CLK
ns
FB_CLK
FB_R/W
FB_TS
FB_OE
S0
S2
S3
DATA
S1
ADDR[31:X]
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
FB_CSn, FB_BE/BWEn
FB_TA
FB3
FB1
FB2
FB7
FB6
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鍙冩暩(sh霉)鎻忚堪
MCF5327CVM240J 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:MPC5XXX RISC 32-BIT CMOS 240MHZ 196-PIN MA-BGA TRAY - Trays
MCF5328 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ColdFire銏� Microprocessor
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MCF53281CVM240 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5329 DRAGONFIRE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
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