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MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
22
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
Figure 7. FlexBus Read Timing
FB4
Data Input Setup
tDVFBCH
3.5
鈥�
ns
FB5
Data Input Hold
tDIFBCH
0鈥�
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4鈥�
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0鈥�
ns
1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, 鈥淒DR SDRAM AC
Timing Characteristics鈥� for SD_CS[3:0] timing.
2 The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
Table 9. FlexBus AC Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
FB_CLK
FB_R/W
S0
S1
S2
S3
FB_TS
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
DATA
ADDR[31:X]
ADDR[23:0]
FB3
FB1
FB2
FB5
FB4
FB7
FB6
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鍙冩暩(sh霉)鎻忚堪
MCF5327CVM240J 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:MPC5XXX RISC 32-BIT CMOS 240MHZ 196-PIN MA-BGA TRAY - Trays
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