參數(shù)資料
型號(hào): MCF52256VN80J
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 33/46頁(yè)
文件大?。?/td> 0K
描述: IC MCU 256KB FLASH 144MAPBGA
標(biāo)準(zhǔn)包裝: 160
系列: MCF5225x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,QSPI,UART/USART,USB OTG
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 144-LBGA
包裝: 托盤
MCF52259 ColdFire Microcontroller, Rev. 5
Electrical Characteristics
Freescale
39
2.16
Equivalent Circuit for ADC Inputs
Figure 14 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is
closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, VREF and the ADC clock frequency.
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8 pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04 pF
3. Equivalent resistance for the channel select mux; 100
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4 pF
5. Equivalent input impedance, when the input is selected =
Figure 14. Equivalent Circuit for A/D Loading
SNR
Signal-to-noise ratio
62 to 66
dB
THD
Total harmonic distortion
75
dB
SFDR
Spurious free dynamic range
67 to 70.3
dB
SINAD
Signal-to-noise plus distortion
61 to 63.9
dB
ENOB
Effective number of bits
9.1
10.6
Bits
1 All measurements are preliminary pending full characterization, and made at V
DD = 3.3 V, VREFH = 3.3 V, and VREFL = ground
2 INL measured from V
IN = VREFL to VIN = VREFH
3 LSB = Least Significant Bit
4 INL measured from V
IN = 0.1VREFH to VIN = 0.9VREFH
5 Includes power-up of ADC and V
REF
6 ADC clock cycles
7 Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
Table 25. ADC Parameters1 (continued)
Name
Characteristic
Min
Typical
Max
Unit
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(VREFH- VREFL)/ 2
125W ESD Resistor
8pF noise damping capacitor
1
(ADC Clock Rate)
(1.410-12)
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