參數(shù)資料
型號: MCF52221
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Microcontroller Data Sheet
中文描述: 微控制器數(shù)據(jù)表
文件頁數(shù): 38/56頁
文件大小: 811K
代理商: MCF52221
MCF52223 ColdFire Microcontroller Data Sheet, Rev. 1
Preliminary
Preliminary Electrical Characteristics
Freescale Semiconductor
38
2.11.1 Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at
the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (V
REFH
-V
REFL
)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V
REFH
-V
REFL
)/2. The switches switch on
every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are
additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the
S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is
that there is an on-going input current, which is a function of the analog input voltage, V
REF
and the ADC
clock frequency.
1.
2.
3.
4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
Equivalent resistance for the channel select mux; 100 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
THD
Total Harmonic Distortion
TBD
-75
dB
SFDR
Spurious Free Dynamic Range
TBD
67 to 70.3
dB
SINAD
Signal-to-Noise plus Distortion
TBD
61 to 63.9
dB
ENOB
Effective Number OF Bits
9.1
10.6
Bits
NOTES:
1
All measurements are preliminary pending full characterization, and were made at V
DD
= 3.3V, V
REFH
= 3.3V, and V
REFL
=
ground
2
INL measured from V
IN
= V
REFL
to V
IN
= V
REFH
3
LSB = Least Significant Bit
4
INL measured from V
IN
= 0.1V
REFH
to V
IN
= 0.9V
REFH
5
Includes power-up of ADC and V
REF
6
ADC clock cycles
7
The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC
Table 30. ADC Parameters
1
(continued)
Name
Characteristic
Min
Typical
Max
Unit
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(V
REFH
- V
REFL )
/ 2
125
ESD Resistor
8pF noise damping capacitor
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