參數(shù)資料
型號: MCF52221
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Microcontroller Data Sheet
中文描述: 微控制器數(shù)據(jù)表
文件頁數(shù): 34/56頁
文件大?。?/td> 811K
代理商: MCF52221
MCF52223 ColdFire Microcontroller Data Sheet, Rev. 1
Preliminary
Preliminary Electrical Characteristics
Freescale Semiconductor
34
2.8
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode, the timing specification for these pins is given in
Table 26
and
Figure 5
.
EXTAL Input High Voltage
External reference
V
IHEXT
2.0
V
DD
V
EXTAL Input Low Voltage
External reference
PLL Lock Time
4,6
Duty Cycle of reference
4
V
ILEXT
V
SS
0.8
V
t
lpll
t
dc
f
UL
f
LCK
C
jitter
500
μ
s
40
60
% f
ref
% f
ref
% f
ref
Frequency un-LOCK Range
- 1.5
1.5
Frequency LOCK Range
CLKOUT Period Jitter
4, 5, 7, 7,8
, Measured at f
SYS
Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
- 0.75
0.75
10
.01
% f
sys
On-chip oscillator frequency
f
oco
7.84
8.16
MHz
NOTES:
1
All internal registers retain data at 0 Hz.
2
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
3
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
f
LOR
with default MFD/RFD settings.
4
This parameter is characterized before qualification rather than 100% tested.
5
Proper PC board layout procedures must be followed to achieve specifications.
6
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
7
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
f
sys
. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via V
DDPLL
and V
SSPLL
and variation in crystal oscillator frequency
increase the Cjitter percentage for a given interval
8
Based on slow system clock of 40 MHz measured at f
sys
max.
Table 26. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
CLKOUT High to GPIO Output Valid
t
CHPOV
t
CHPOI
t
PVCH
t
CHPI
-
10
ns
G2
CLKOUT High to GPIO Output Invalid
1.5
-
ns
G3
GPIO Input Valid to CLKOUT High
9
-
ns
G4
CLKOUT High to GPIO Input Invalid
1.5
-
ns
Table 25. PLL Electrical Specifications (continued)
(V
DD
and V
DDPLL
= 2.7 to 3.6 V, V
SS
= V
SSPLL
= 0 V)
Characteristic
Symbol
Min
Max
Unit
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