參數(shù)資料
型號: MC9S12KC128CPU
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Microcontrollers
中文描述: 微控制器
文件頁數(shù): 78/126頁
文件大?。?/td> 7307K
代理商: MC9S12KC128CPU
Device User Guide — 9S12KT256DGV1/D V01.09
78
Freescale Semiconductor
5.3 Resets
Resets are a subset of the interrupts featured in
Table 5-1
. The different sources capable of generating a
system reset are summarized in
Table 5-2
.
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode
dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
Refer to
Table 1-2(Table 1-2)
for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit.
When the CPU12 Reference Manual refers to
cycles
this is equivalent to
Bus Clock periods
.
So
1 cycle
is equivalent to
1 Bus Clock period
.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module.
When the BDM Block Guide refers to
alternate clock
this is equivalent to
Oscillator Clock
.
Table 5-2 Reset Summary
Reset
Priority
1
1
1
2
3
Source
CRG Module
RESET pin
VREG Module
CRG Module
CRG Module
Vector
Power-on Reset
External Reset
Low Voltage Reset
Clock Monitor Reset
COP Watchdog Reset
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
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