參數(shù)資料
型號： MC9S12C32MFU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 58/94頁
文件大?。?/td> 906K
代理商： MC9S12C32MFU
Device User Guide — 9S12C32DGV1/D V01.01
61
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics In 5V Range
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA
≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
NOTE:
VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the
internal VRL pad is bonded to the VSSA pin.
A.2.2 ATD Operating Characteristics In 3.3V Range
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped
Table A-8 ATD Operating Characteristics 5V Range
Conditions are shown in Table A-4 unless otherwise noted. 5V-10% <= VDDA <= 5V+10%
Num
Rating
Symbol
Min
Typ
Max
Unit
1
Reference Potential
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA
V
2
Differential Reference Voltage1
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
VRH-VRL
4.75
5.0
5.25
V
3
ATD Clock Frequency
fATDCLK
0.5
2.0
MHz
4
ATD 10-Bit Conversion Period
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
NCONV10
TCONV10
14
7
28
14
Cycles
s
5
Recovery Time (VDDA=5.0 Volts)
tREC
20
s
6
Reference Supply current
IREF
0.75
mA
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