參數(shù)資料
型號(hào): MC9S12C32MFU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁(yè)數(shù): 37/94頁(yè)
文件大?。?/td> 906K
代理商: MC9S12C32MFU
Device User Guide — 9S12C32DGV1/D V01.01
42
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM).
6.1 Device-specific information
6.1.1 PPAGE
External paging is not supported on this device. In order to access the 16K Flash Block1 in the address
range $8000-$BFFF the PPAGE register must be loaded with a valid value for this range. Valid PPAGE
values for Flash Block1 visibility in the $8000-$BFFF range are PPAGE=$38, $3A, $3C, $3E.
Flash Block1 is also visible in the $4000-$7FFF range if ROMHM is cleared.
Flash Block2 is visible in the $8000-$BFFF range with PPAGE=$39, $3B, $3D, $3F.
Flash Block2 is always visible in the range $C000-$FFFF if ROMON is set.
Section 7 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
7.1 Device-specific information
The VREG is part of the IPBus domain.
7.1.1 VREGEN
VREGEN is connected internally to VDDR.
7.1.2 VDD1, VDD2, VSS1, VSS2
In the 80 pin QFP package version, both internal VDD and VSS of the 2.5V domain are bonded out on 2
sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected
together internally. VSS1 and VSS2 are connected together internally.
The extra pin pair enables systems using the 80 pin package to employ better supply routing and further
decoupling.
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