參數(shù)資料
型號(hào)： MC9S12C32MFU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 16/94頁(yè)
文件大?。?/td> 906K
代理商： MC9S12C32MFU
Device User Guide — 9S12C32DGV1/D V01.01
23
Section 2 Signal Description
2.1 Signal Properties Summary
Table 2-1 MC9S12C32 Power and Ground Connection Summary
NOTE:
All VSS pins must be connected together in the application. Because fast signal
transitions place high, short-duration current demands on the power supply, use
bypass capacitors with high-frequency characteristics and place them as close to
the MCU as possible. Bypass requirements depend on MCU pin load.
Table 2-2 Signal Properties
Mnemonic
Nominal
Voltage
Description
VDD1
VDD2
2.5 V
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and bypass
the internal voltage regulator.
In the 48 and 52 LQFP packages VDD2 and VSS2 are not available.
VSS1
VSS2
0V
VDDR
5.0 V
External power and ground, supply to internal voltage regulator.
To disable voltage regulator attach VDDR to VSSR.
VSSR
0 V
VDDX
5.0 V
External power and ground, supply to pin drivers.
VSSX
0 V
VDDA
5.0 V
Operating voltage and ground for the analog-to-digital converters and the
reference for the internal voltage regulator, allows the supply voltage to the
A/D to be bypassed independently.
VSSA
0 V
VRH
5.0 V
Reference voltage low for the ATD converter.
In the 48 and 52 LQFP packages VRL is bonded to VSSA.
VRL
0 V
VDDPLL
2.5 V
Provides operating voltage and ground for the Phased-Locked Loop. This
allows the supply voltage to the PLL to be bypassed independently.
Internal power and ground generated by internal regulator.
VSSPLL
0 V
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Description
Reset
State
Power
Domain
EXTAL
—
Oscillator pins
Input
VDDPLL
XTAL
—
Output
VDDPLL
RESET
—
External reset pin
Input
VDDX
XFC
—
PLL loop lter pin
N/A
VDDPLL
BKGD
MODC
TAGHI
Background debug, mode pin, tag signal high
Input
VDDX
TEST
VPP
—
Test pin only
Input
VSSX
PE7
NOACC
XCLKS
Port E I/O pin, access, clock select
Input
VDDX
PE6
IPIPE1
MODB
Port E I/O pin and pipe status
Input
VDDX
PE5
IPIPE0
MODA
Port E I/O pin and pipe status
Input
VDDX
PE4
ECLK
—
Port E I/O pin, bus clock output
Input
VDDX
PE3
LSTRB
TAGLO
Port E I/O pin, low strobe, tag signal low
Input
VDDX
PE2
R/W
—
Port E I/O pin, R/W in expanded modes
Input
VDDX
PE1
IRQ
—
Port E input, external interrupt pin
Input
VDDX
PE0
XIRQ
—
Port E input, non-maskable interrupt pin
Input
VDDX
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