參數(shù)資料
型號(hào): MC9328MX1VM15
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù): 93/100頁(yè)
文件大?。?/td> 1267K
代理商: MC9328MX1VM15
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
92
Freescale Semiconductor
4.17
CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32
× 32 image data receive
FIFO, and a 16
× 32 statistic data FIFO.
4.17.1
Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 69 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 42.
Figure 68. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
2 There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 – PC24). When SSI signals
are configured as outputs, they can be viewed at Port C alternate function a. When SSI signals are configured as inputs, the
SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input is selected
from Port C alternate function.
3
bl = bit length; wl = word length
VSYNC
HSYNC
PIXCLK
DATA[7:0]
Valid Data
2
1
7
5
6
3
4
Valid Data
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX1
Product
Family
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