- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45284 > MC9328MX1VM15 (FREESCALE SEMICONDUCTOR INC) 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC9328MX1VM15 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256 |
| 文件頁數(shù)： | 35/100頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | MC9328MX1VM15 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
Signals and Connections
MC9328MX1 Technical Data, Rev. 7
4
Freescale Semiconductor
Negated
means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
2
Signals and Connections
Table 2 identifies and describes the i.MX1 processor signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. i.MX1 Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
Address bus signals
D[31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16].
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8].
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
OE
Memory Output Enable—Active low output enables external data bus.
CS [5:0]
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input
signal by external DRAM.
DTACK
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MX1 processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals
are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX1
Product
Family
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9328MX1CVM15R2 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MX1VM20R2 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MX1CVM15 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MX1VM15R2 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MX1VM20R2 | 200 MHz, RISC PROCESSOR, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX1VM15R2 | 功能描述:IC MCU I.MX 150MHZ 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX1 標(biāo)準(zhǔn)包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:8KB（8K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285 |
| MC9328MX1VM20 | 功能描述:處理器 - 專門應(yīng)用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX1VM20R2 | 功能描述:處理器 - 專門應(yīng)用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21_06 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。