參數(shù)資料
型號(hào)： MC9328MX1VM15
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù)： 92/100頁(yè)
文件大?。?/td> 1267K
代理商： MC9328MX1VM15
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
91
11b
STCK high to STXD low
2.51
3.99
2.2
3.5
ns
12
STCK high to STXD high impedance
12.43
14.59
10.9
12.8
ns
13
SRXD setup time before SRCK low
20
–
17.5
–
ns
14
SRXD hold time after SRCK low
0–0–
ns
External Clock Operation (Port C Alternate Function)2
15
STCK/SRCK clock period1
92.8
–
81.4
–
ns
16
STCK/SRCK clock high period
27.1
–
40.7
–
ns
17
STCK/SRCK clock low period
61.1
–
40.7
–
ns
18
STCK high to STFS (bl) high3
–92.8081.4
ns
19
SRCK high to SRFS (bl) high3
–92.8081.4
ns
20
STCK high to STFS (bl) low3
–92.8081.4
ns
21
SRCK high to SRFS (bl) low3
–92.8081.4
ns
22
STCK high to STFS (wl) high3
–92.8081.4
ns
23
SRCK high to SRFS (wl) high3
–92.8081.4
ns
24
STCK high to STFS (wl) low3
–92.8081.4
ns
25
SRCK high to SRFS (wl) low3
–92.8081.4
ns
26
STCK high to STXD valid from high impedance
18.9
29.07
16.6
25.5
ns
27a
STCK high to STXD high
9.23
20.75
8.1
18.2
ns
27b
STCK high to STXD low
10.60
21.32
9.3
18.7
ns
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hole time after SRCK low
0–0–
ns
Synchronous Internal Clock Operation (Port C Alternate Function)2
31
SRXD setup before STCK falling
18.81
–
16.5
–
ns
32
SRXD hold after STCK falling
0–0–
ns
Synchronous External Clock Operation (Port C Alternate Function)2
33
SRXD setup before STCK falling
1.14
–
1.0
–
ns
34
SRXD hold after STCK falling
0–0–
ns
1 All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted
frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid
by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 41. SSI 2 (Port C Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX1
Product
Family
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