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| 型號： | MC9328MX1VH20R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 200 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256 |
| 文件頁數(shù)： | 56/96頁 |
| 文件大小： | 1486K |
| 代理商： | MC9328MX1VH20R2 |
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MC9328MX1 Advance Information, Rev. 4.1
6
Freescale Semiconductor
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [24:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16]
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8]
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]
OE
Memory Output Enable—Active low output enables external data bus
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by
the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on
SDRAM/SyncFlash cycles.
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| MC9328MX1VM15 | 功能描述:IC MCU I.MX 150MHZ 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX1 標(biāo)準(zhǔn)包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲器容量:8KB（8K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285 |
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| MC9328MX1VM20 | 功能描述:處理器 - 專門應(yīng)用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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| MC9328MX21 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors |
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