參數(shù)資料
型號: MC9328MX1DVM20R2
廠商: Freescale Semiconductor
文件頁數(shù): 74/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX 200MHZ 256-MAPBGA
標(biāo)準包裝: 1
系列: i.MX1
核心處理器: ARM9
芯體尺寸: 32-位
速度: 200MHz
連通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 110
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -30°C ~ 70°C
封裝/外殼: 256-MAPBGA
包裝: 剪切帶 (CT)
其它名稱: MC9328MX1DVM20R2CT
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
75
Figure 54. SDIO ReadWait Timing Diagram
4.11
Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
DAT[1]
For 4-bit
DAT[2]
For 4-bit
CMD
******
P S T
E Z Z
******
CMD52
Z
CRC
E Z Z
S
Block Data
L L L L L L L L L L L L L L L L L L L L L H Z S
E
S
Block Data
E
Block Data
Z Z L H
E
S
Block Data
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