參數(shù)資料
型號: MC9328MX1DVM20R2
廠商: Freescale Semiconductor
文件頁數(shù): 29/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX 200MHZ 256-MAPBGA
標準包裝: 1
系列: i.MX1
核心處理器: ARM9
芯體尺寸: 32-位
速度: 200MHz
連通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 110
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -30°C ~ 70°C
封裝/外殼: 256-MAPBGA
包裝: 剪切帶 (CT)
其它名稱: MC9328MX1DVM20R2CT
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
34
Freescale Semiconductor
4.4.2.4
WAIT Write Cycle DMA Enabled
Figure 9. WAIT Write Cycle DMA Enabled
7
Wait asserted to RW negated
1T+2.15
2T+7.34
ns
8
Data hold timing after RW negated
2.5T-1.18
ns
9
Data ready after CS5 is asserted
T
ns
10
EB negated after CS5 is negated
1.5T+0.74
1.5T+2.35
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
OE
WAIT
Address
EB
CS5
RW
(logic high)
DATABUS
programmable
min 0ns
programmable
min 0ns
8
5
7
11
12
4
1
2
3
10
6
13
9
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