參數(shù)資料
型號(hào)： MC9328MX1DVM20R2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 73/100頁(yè)
文件大?。?/td> 0K
描述： IC MCU I.MX 200MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝： 1
系列： i.MX1
核心處理器： ARM9
芯體尺寸： 32-位
速度： 200MHz
連通性： EBI/EMI，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 110
程序存儲(chǔ)器類(lèi)型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.7 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -30°C ~ 70°C
封裝/外殼： 256-MAPBGA
包裝： 剪切帶 (CT)
其它名稱(chēng)： MC9328MX1DVM20R2CT
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
74
Freescale Semiconductor
4.10.2
SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the “Interrupt
Period” during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
Figure 53. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps
the clock running, and allows the user to submit commands as normal. After all commands are submitted,
the user can switch back to the data transfer operation and all counter and status values are resumed as
access continues.
Command read cycle
NRC
8
–
Clock cycles
Command-command cycle
NCC
8
–
Clock cycles
Command write cycle
NWR
2
–
Clock cycles
Stop transmission cycle
NST
2
Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC100) defined in CSD register bit[111:104]
Table 30. Timing Values for Figure 48 through Figure 52 (Continued)
Parameter
Symbol
Minimum
Maximum
Unit
Interrupt Period
IRQ
DAT[1]
For 4-bit
L H
Interrupt Period
DAT[1]
For 1-bit
CMD
Content
S T
E Z Z P
E Z Z
******
Z Z
Response
CRC
S
Z
E
S
Block Data
E
S
Block Data
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