參數(shù)資料
型號(hào): MC9328MX1DVM20R2
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù): 87/94頁(yè)
文件大小: 1487K
代理商: MC9328MX1DVM20R2
88
MC9328MX1 Advance Information
MOTOROLA
Specifications
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
3.21.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 71 on page 89 shows the timing
diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to
received data in negative edge. The parameters for the timing diagrams are listed in Table 43 on page 89.
Figure 70. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
PIXCLK
DATA[7:0]
23
6
4
5
Valid Data
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