參數(shù)資料
型號(hào)： MC9328MX1DVM20R2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 200 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù)： 69/94頁(yè)
文件大?。?/td> 1487K
代理商： MC9328MX1DVM20R2
Specifications
MOTOROLA
MC9328MX1 Advance Information
71
3.17 SDRAM Memory Controller
A write to an address within the memory region initiates the program sequence. The first command issued
to the SyncFlash is Load Command Register. A [7:0] determine which operation the command performs.
For this write setup operation, an address of 0x40 is hardware generated. The bank and other address lines
are driven with the address to be programmed. The next command is Active which registers the row
address and confirms the bank address. The third command supplies the column address, re-confirms the
bank address, and supplies the data to be written. SyncFlash does not support burst writes, therefore a
Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash
is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register
operation. The bank and other address lines are driven to the selected address. The second command is
Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
4a
Output delay time1
5.7
–
5
–
ns
4b
Output setup time1
5.7
–
5
–
ns
1.
CL of PWMO = 30 pF
Table 33. PWM Output Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
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