參數(shù)資料
型號(hào): MC9328MX1DVM20R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù): 20/94頁
文件大小: 1487K
代理商: MC9328MX1DVM20R2
Specifications
MOTOROLA
MC9328MX1 Advance Information
27
3.8.2.4 DTACK Write Cycle DMA Enabled
Figure 9. DTACK Write Cycle DMA Enabled
Table 17. WSC = Parameters for Write Cycle 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
ns
2EB assertion time
See note 2
ns
3CS5 pulse width
3T
ns
4RW negated before CS5 is negated
1.5T+0.58
1.5T+1.58
ns
5
Address inactive before CS negated
0.93
ns
6
DTACK asserted after CS5 asserted
1019T
ns
7
DTACK asserted to RW negated
2T+1.8
3T+5.26
ns
8
Data hold timing after RW negated
1.5T-0.59
ns
9
Data ready after CS5 is asserted
T
ns
10
CS deactive to next CS active
T
ns
11
EB negate to CS negate
0.5T+0.74
0.5T+2.17
ns
12
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
OE
DTACK
Address
EB
CS5
RW
(logic high)
Databus
programmable
min 0ns
programmable
min 0ns
(1)
(2)
(7)
(8)
(4)
(5)
(3)
(6)
(9)
(output from MX1)
(10)
(11)
(12)
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