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參數(shù)資料
| 型號： | MC92603VM |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH TXRX QUAD GIG 256-MAPBGA |
| 標準包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-MAPBGA |
| 包裝： | 托盤 |
MOTOROLA
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
13
GMII Interface
GMII Mode is enabled by setting the TBIE input low and COMPAT input high. When in this mode the
receiver should be connected to a standard Gigabit Ethernet MAC as shown in Table 9.
Initially the receiver must attain byte alignment through the detection of 4 COMMA code groups with the
same alignment as explained previously. Next the receiver must attain stream alignment per Figure 36-9 of
‘IEEE Std 802.3-2002.’
The RECV_x_ERR output remains high until both alignments are attained.
The receiver will now search for a Start_of_Packet code group (/S/). Upon the detection of a Start_of_Packet
the receiver will replace that code group with a preamble code group (55 hex) and present this data on the
receiver data output RECV_x_7 through RECV_x_0 as the RECV_x_DV output is raised. This is per
Figures 36-7a and 36-7b of ‘IEEE Std 802.3-2002.’
Data will continue to be presented on the data outputs and the RECV_x_DV output will remain high until
an End_of_Packet code group (/T/) is received. At this point the RECV_x_DV output will lowered and
remain low until the next Start_of_Packet is received. When the End_of_Packet code group (/T/) is received
the RECV_x_DV output will lowered after the previous data code group is presented on the receiver data
interface (RECV_x_7 through RECV_x_0).
TBI Interface
TBI Mode is enabled by setting the TBIE and COMPAT inputs high. When in this mode, the MC92603 will
conform to the IEEE Std 802.3-2002 TBI interface signals and protocol. The complete TBI connection to
a standard Ethernet MAC is show in
Table 9. GMII Connection to Standard Ethernet MAC
IEEE 802.3_2002 Signal
Name
Function
Direction
(relative to GEt)
GEt Port Name
GTX_CLK
Transmit Clock
Input
XMIT_x_CLK
TX_EN
Transmit Enable
Input
XMIT_x_ENABLE
TX_ER
Force Error on Transmitted Byte
Input
XMIT_x_ERR
TXD<7:0>
Transmit Data
Input
XMIT_x_[7:0]
RX_CLK
Receive Clock
Output
RECV_x_CLK
RXD<7:0>
Receive Data
Output
RECV_x_[7:0]
RX_ER
Receiver has detected an error
Output
RECV_x_ERR
RX_DV
Receiver has detected data
Output
RECV_x_DV
MDC
Management Data Clock
Input
MD_CLK
MDIO
Management Data Input/Output
Bidirectional
MD_DATA
The following inputs must be externally pulled up/down as indicated
Pull Up
Management Interface Enable
Input
MD_ENABLE
Variable (PUP/PUD)
MDIO PHY Address
Input
MD_ADR[4:2]
Pull Down
Disable unused Transmitter Input
Input
XMIT_x_K
Pull Down
Conguration Input - put in 8 bit mode
Input
TBIE
Pull Up
Conguration Input - put in
synchronized mode
Input
BSYNC
Pull Down
Conguration Input - disable word
alignment
Input
WSYNC1 & WSYNC0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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