參數(shù)資料
型號(hào): MC92603VM
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: IC ETH TXRX QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-MAPBGA
包裝: 托盤
4
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figure 2. Phy and Backplane Application
Functional Summary
The transceivers send/receive differential data in one of two operating ranges. They may be operated in the
high range with a maximum data rate of 1 Gbps (1.25 gigabaud) or at a half-rate of 500 Mbps (625
megabaud). The data transfer rate is determined by the state of the half speed enable (HSE) input and the
frequency of the reference clock. Any frequency and resulting data rate with in the ranges shown in Table 1
may be used.
The reference clock inputs are differential LVPECL. Optionally, a single ended 3.3 Volt (LVCMOS/LVTTL)
input clock source may be used.
Table 1. Legal Reference Clock Frequency Ranges
HSE
Reference Frequency
Min. (MHz)
Reference Frequency
Max (MHz)
Link Transfer Rate
(Gigabaud)
Low
95.00
135.0
0.95 - 1.35
High
47.50
67.50
0.475 - 0.675
MC92603
Fiber
Backplane
MC92603
Switch Fabric Card
TBI/RTBI
Line Card – 4 Port – 1000BASE-X
GMII/RGMII
MC92603
Quad
Backplane
SERDES
Mac
Processors/
Memory/
ASICs
MAC
MC92603
Quad
Ethernet
PHY
Fiber
E/O
Line Card Application
with both
Gigabit Ethernet PHY
and
Backplane Applications
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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