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參數(shù)資料
| 型號(hào)： | MC92603VM |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH TXRX QUAD GIG 256-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-MAPBGA |
| 包裝： | 托盤 |
MOTOROLA
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Transmitter Functionality
The MC92603 and MC92604 are versatile devices that may be used in backplane or Ethernet PHY
applications. They may be congured in multiple data interface and operational modes. The following
sections provide a basic functional description of the transmitter, its operational modes and data interfaces.
Each transmitter takes data presented at its source synchronous parallel data input port, creates a
transmission code group or character (if not pre-encoded), and serially transmits the code group out of the
differential link output pads.
The transmitter driver is a controlled impedance driver. The impedance of the driver is programmable to 50-
or 75-
through the MEDIA conguration signal. Drive impedance is 50- when MEDIA is low and 75-
when high.
Interface Conguration
The transmitter may operate in one of eight data interface congurations as shown in Table 2. The
compatibility conguration pin, COMPAT, establishes operation in either the “backplane” mode or the
“Ethernet” compatible mode. The ten bit interface enable, TBIE, conguration input determines if the
internal 8B/10B encoder will be used with uncoded input data or bypassed for a pre-encoded (coded) input
data. The DDR conguration pin when enabled “reduces” the interface from an 8-/10-bit single data rate
interface to a 4-/5-bit double data rate interface.
The conguration signals, TBIE and COMPAT, also affect the receiver’s conguration.
Transmit data is sampled and stored in the input FIFO on the rising edge (single data rate) of the appropriate
transmit clock, if DDR is low, or both edges (double data rate) of the transmit clock if DDR is high. The
FIFO accepts data to be transmitted and synchronizes it to the internal clock domain.
The transmitter data interface operates at high frequency (nominally 125MHz). In order to ease
development of devices that interface with the Gigabit Ethernet transceivers, all transmitter data input
interfaces are source synchronous. The data for each channel has its own dedicated clock input. This allows
the clock at the source of the data to be routed with the data ensuring matched delay and timing. However,
if per-channel clock sources are not available or deemed unnecessary, all channels may be clocked by a
common clock source. The transceivers may be congured so that the channel A transmit clock is used as
the source synchronous clock for all four channels. All transmitter clock inputs and the reference clock
inputs must have identical frequencies, however, a phase shift of +/- 180o is tolerated.
Table 2. MC92603 Data Interface Modes
Data Interface Mode
COMPAT
TBIE
DDR
Backplane 8-bit Uncoded Data
Low
Backplane (4-bit reduced interface) Uncoded Data
Low
High
Backplane 10-bit Coded Data
Low
High
Low
Backplane (5-bit reduced interface) Coded Data
Low
High
Ethernet compatible GMII
High
Low
Ethernet compatible RGMII
High
Low
High
Ethernet compatible TBI
High
Low
Ethernet compatible RTBI
High
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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